When lines of interconnection between two circuits are relatively long or the circuits sufficiently fast such that the rise/fall times of signals exchanged between the circuits are comparable with propagation times over the connection line, then interconnection lines must be treated as long transmission lines. Therefore, the line must be properly matched, at least at one end thereof, otherwise signals sent on the line will be reflected to some extent and make transmissions complicated. Impedance mismatchings may be accepted as far as the consequent increase of the time required for reaching steady-state conditions remains inconsequential.
In CMOS buffers, the more convenient matching is carried out at the input end of the line (null DC power consumption), that is, making the output impedance Zout of the line driving buffer equal to the characteristic impedance Z0 of the transmission line. The line load may be represented by a capacitance electrically in parallel with a current generator (typically Iol=−Ioh≦100 μA). When the load capacitance is very small (on the order of pF) the line practically works in open circuit condition. Often the line is not matched at its output end and transmitted signals are reflected.
The reflected wavefront upon reaching the input end of the line sees a dynamic impedance that corresponds to a reversed replica of the instantaneous slope of the output characteristic id=f(vds) of the line driver. Of course, if the output dynamic impedance of the line driving buffer is equal to the characteristic impedance of the line, the wavefront is not reflected back towards the output end of the line. In contrast, a new reflected wave towards the output end is produced, and so on. It is evident that the ability of keeping constant the slope of the output characteristic id=f(vds) instant by instant, over the whole swing of the output voltage Vout, is a desirable characteristic of the driver.
FIG. 1 depicts a typical conventional CMOS output buffer. The inverters IV1 and IV2 that drive the gates of the output drivers MP1, MN1 are all provided with gate slew limiters (GSLs) that control the speed of gate signals to limit switching noise on the supply lines and on the lines connecting to ground. These GSLs may be integrated resistors or typically adjustable resistances in the form of a transistor the on-resistance of which is fixed by applying a certain bias voltage to the gate node of the transistor.
This buffer does not satisfy the above mentioned requirements because its output impedance is too large compared to typical values of the characteristic line impedance Z0, as far as the output transistors operate in the saturation region. Only when the output transistors operate in the linear region, the output impedance almost becomes equal to Z0.
To address operating conditions it has been proposed to electrically connect a complementary diode-connected MOS transistor in parallel to each driver, that will be in a conduction state as far as |Vds|=|Vgs|≧|Vth|. Enhancement MOS transistors are commonly used for realizing the buffer output stage. They are characterized by a relatively large threshold (≈0.9V, considering also the “body effect”) thus the output buffer characteristic is a piecewise function. An example is shown in FIG. 2, for the case of the “pull up” transistor (bold line). The problem is generally overcome by boosting the driving signals of the gates of the added complementary MOS, even if this implies a significant increase of circuit complexity and an increased silicon area overhead (pump capacitors), the amount of which is comparable with the silicon area occupied by the output MOS transistor.
A further development, in terms of linearity, is obtained with the method described in the published U.S. patent application No. 2002/0158674. According to the disclosed method, the voltage Vgs of the common source drivers is modulated by the output voltage of the buffer. In particular, when Vout increases, the transistor is forced to work with a decreased Vgs. The result is a linearized dynamic characteristic as the one depicted with a dashed line in FIG. 2.
FIG. 3 depicts in a simplified fashion the circuit that implements the method disclosed in the above publication for the “pull up” side of the output buffer. The output signal Vout switches from low to high, the voltage C is equal to Vcc, the voltage B is null (ground) and the voltage A is left floating (high impedance). The MOS transistors MP2 and MN3 are the pull-up side of the output stage of the buffer, the N-channel MOS MN2 works as a source follower on a load composed of the pair MP1, MN1. The source follower, coupled to the output node, is part of a negative feedback loop of the driver MP2.
The characteristic may be considered linear based upon the faster the response speed and thus the larger the current consumption of the feedback circuit. Such a large power consumption could make it difficult to satisfy the power consumption specifications in stand-by when the output buffers are active (i.e. not in tristate condition). Besides for meeting response speed specifications, the power consumption of the above-mentioned feedback circuit is due to the need of ensuring an adequate overdrive Vgs-Vth to the driver (it must remain turned on), especially if the driver must deliver the current Ioh (or Iol).
These reasons may contrast with stringent requirements of reduced power consumption, for example in nonvolatile memory devices but also in many other applications with some requisites. Moreover, from the characteristics depicted in FIG. 2, it is evident that, in the linear functioning region of the characteristics, the common source MOS has a smaller output resistance than the required resistance, thus the drivers are over-sized, with a larger silicon area consumption.